1. Field of the Disclosure
The present disclosure relates to electronic devices and processes, and more particularly to an electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and processes for forming the same.
2. Description of the Related Art
State-of-the-art semiconductor devices currently include transistors having a gate dielectric layer with one or more high dielectric constant (“high-k”) materials. These materials typically have a dielectric constant higher than the silicon nitride, which is approximately seven. Conventional transistors include N+ or P+ doped silicon gate electrodes. One or more problems can occur when a silicon layer contacts a high-k gate dielectric layer. A high-k gate dielectric layer can include a metal oxide, such as ZrO2. When ZrO2 contacts silicon at an elevated temperature, such as during a source/drain anneal, silicon (e.g., from the substrate or a subsequently-formed polysilicon gate electrode) can react with at least some of the zirconium to form ZrSi2, which is conductive. In addition, some of the dopant from the N+ or P+ silicon can migrate from the silicon into the gate dielectric layer or other parts of the transistor. The dopant concentration at the silicon-gate dielectric interface becomes depleted, thereby forming a more resistive portion, which electronically, reduces the electrically measured capacitance of the gate dielectric layer within the transistor, which is undesired.
High-k dielectric materials, including HfO2, ZrO2, etc., when used as a gate dielectric layer typically have metal gate electrodes, due to the potential problems when high-k dielectric materials contact silicon and potential dopant migration into the gate dielectric layer. Exemplary materials for metal gate electrodes include TiN, TaC, TaSiN, and the like.
When a metal gate electrode is used, the portion of metal gate electrode closest to the gate dielectric layer establishes the work function for the gate electrode. An NMOS transistor may have TaSiN as the portion of its metal-containing gate electrode closest to the high-k gate dielectric layer, and a PMOS transistor may have TiN as the portion of its metal-containing gate electrode closest to the high-k gate dielectric layer. The work function for TaSiN is 4.3 eV, and the work function for TiN is 4.6 eV. As a basis for comparison, the work function for N+ silicon and the energy level for the conduction band (“Ec”) for silicon is 4.1 eV, and the work function for P+ silicon and the energy level for the valence band (“Ev”) for silicon is 5.2 eV. Therefore, the difference between Ec and the work function for TaSiN is 0.2 eV, and the difference between Ev and the work function for TiN is 0.6 eV. These differences can cause longer times to switch states (i.e., “on” and “off”) for the transistors, and therefore, result in a slower operating electronic device.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.